Dr. Frank Greer – Patents (Pending and Approved)
Publication number: 20240102167
Abstract: A boat used in a chemical vapor deposition (CVD) furnace is configured to hold one or more complex three-dimensional (3D) structures when performing a coating. A platform wafer is placed horizontally in the boat to support the complex 3D structures and a mount is positioned to secure the complex 3D structures on the platform wafer during the CVD process. One or more “witness” wafers may also be placed in the boat for analyzing the thin-film coating. The platform wafer may be positioned between or bracketed by the vertical wafers. Parts with coatings manufactured using LPCVD are further disclosed.
Type: Application
Filed: September 28, 2023
Publication date: March 28, 2024
Applicant: California Institute of Technology
Inventors: Matthew R. Dickie, Su C. Chi, Billy Chun-Yip Li, William C. West, Harold Frank Greer
Patent number: 11890640
Abstract: Methods of forming a monolayer of nanoparticles are described. The method may include forming an activated surface on a substrate. Methods may also include contacting the activated surface with a fluid including nanoparticles. Methods may further include forming a plurality of monolayers in the liquid on the activated surface. The plurality of nanoparticles may include a first monolayer of nanoparticles bonded to the activated surface. The plurality of nanoparticles may include a second monolayer of nanoparticles bonded to the first monolayer of nanoparticles. The bond strengths between a nanoparticle and the underlying substrate, between adjacent nanoparticles, and between nanoparticles of adjacent monolayers may be related by a specific relationship. The method may also include removing monolayers of the plurality of monolayers while retaining the first monolayer to form the substrate with the first monolayer. Systems for performing the methods and substrates resulting from the methods are also described.
Type: Grant
Filed: January 21, 2021
Date of Patent: February 6, 2024
Assignee: Nanoclear Technologies, Inc.
Inventors: Harold Frank Greer, Rehan Kapadia, Angelica Saenz, David Webber
Publication number: 20240021428
Abstract: A method for processing a surface, comprising obtaining a substrate comprising an epitaxially grown semiconductor; reacting a surface of the semiconductor and/or a surface of a dielectric layer on the semiconductor, with a reactant comprising a gas or a plasma, to form a reactive layer on the dielectric layer and/or the semiconductor, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer or the semiconductor; and processing (e.g.
Type: Application
Filed: July 13, 2023
Publication date: January 18, 2024
Applicants: California Institute of Technology, University of Southern California
Inventors: Harold Frank Greer, Rehan Kapadia, Debargyha Sarkar
Patent number: 11864472
Abstract: A method for etching a surface including obtaining a structure comprising a plurality of nanowires on or above a substrate and a dielectric layer on or above the nanowires, wherein the dielectric layer comprises protrusions formed by the underlying nanowires; reacting a surface of the dielectric layer with a reactant, comprising a gas or a plasma, to form a reactive layer on the dielectric layer, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer and the reactive layer comprises sidewalls defined by the protrusions; and selectively etching the reactive layer, wherein the etching etches the protrusions laterally through the sidewalls so as to planarize the surface and remove or shrink the protrusions.
Type: Grant
Filed: July 12, 2021
Date of Patent: January 2, 2024
Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
Inventors: Harold Frank Greer, Andrew D. Beyer, Matthew D. Shaw, Daniel P. Cunnane
Publication number: 20230151495
Abstract: Methods described herein allow for a smoothing of a particular material on a substrate independently of smoothing a different material on the substrate. Both materials may be exposed to the same reactant but form different skins (e.g., reactive layers). One skin may allow for smoothing of one material, while the other skin may protect or preserve the underlying material. Removing one of the skins may result in a smoother underlying material. The skins may be formed by a dry process and removed by a wet process, or the skins may be formed by a wet process and removed by a dry process. The change of the reaction medium between wet and dry for reaction and removal may allow for highly selective chemistries to result in smoothing one material while not affecting the underlying substrate or other materials at the surface. Substrates produced by these methods are described herein.
Type: Application
Filed: November 16, 2022
Publication date: May 18, 2023
Inventors: Harold Frank Greer, Rehan Kapadia
Publication number: 20230129191
Abstract: Disclosed herein is a method of producing an infrared detector. In certain embodiments, the method includes: forming a planar multi-layer structure including an absorber including a superlattice structure; patterning the planar multi-layer structure; etching the planar multi-layer structure to define a plurality of pixels, the sidewalls of the plurality of pixels includes a sidewall roughness and multiple types of surface oxides; and performing a surface treatment process to the plurality of pixels in order to reduce the sidewall roughness and replace the surface oxides with a chlorinated surface morphology. The surface treatment process may reduce surface current of the infrared detector which may decrease the dark current in the infrared detector.
Type: Application
Filed: October 25, 2022
Publication date: April 27, 2023
Applicant: California Institute of Technology
Inventors: Cory J. Hill, Harold Frank Greer
Publication number: 20230095274
Abstract: Methods of forming a monolayer of nanoparticles are described. The method may include forming an activated surface on a substrate. Methods may also include contacting the activated surface with a fluid including nanoparticles. Methods may further include forming a plurality of monolayers in the liquid on the activated surface. The plurality of nanoparticles may include a first monolayer of nanoparticles bonded to the activated surface. The plurality of nanoparticles may include a second monolayer of nanoparticles bonded to the first monolayer of nanoparticles. The bond strengths between a nanoparticle and the underlying substrate, between adjacent nanoparticles, and between nanoparticles of adjacent monolayers may be related by a specific relationship. The method may also include removing monolayers of the plurality of monolayers while retaining the first monolayer to form the substrate with the first monolayer. Systems for performing the methods and substrates resulting from the methods are also described.
Type: Application
Filed: January 21, 2021
Publication date: March 30, 2023
Inventors: Harold Frank GREER, Rehan KAPADIA, Angelica SAENZ, David WEBBER
Publication number: 20220028907
Abstract: A method for forming a composite substrate containing layers of dissimilar materials is provided. The method includes a step of disposing a release layer over a base substrate where the base substrate is composed of a first material. A template layer is attached to the release layer. Characteristically, the template layer is composed of a second material and adapted to form a compound semiconductor device thereon.
Type: Application
Filed: July 26, 2021
Publication date: January 27, 2022
Applicants: UNIVERSITY OF SOUTHERN CALIFORNIA, CALIFORNIIA INSTITUTE OF TECHNOLOGY, InPi, LLC
Inventors: Rehan Rashid KAPADIA, Khaled AHMED, Frank GREER
Publication number: 20220013706
Abstract: A method for etching a surface including obtaining a structure comprising a plurality of nanowires on or above a substrate and a dielectric layer on or above the nanowires, wherein the dielectric layer comprises protrusions formed by the underlying nanowires; reacting a surface of the dielectric layer with a reactant, comprising a gas or a plasma, to form a reactive layer on the dielectric layer, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer and the reactive layer comprises sidewalls defined by the protrusions; and selectively etching the reactive layer, wherein the etching etches the protrusions laterally through the sidewalls so as to planarize the surface and remove or shrink the protrusions.
Type: Application
Filed: July 12, 2021
Publication date: January 13, 2022
Applicant: California Institute of Technology
Inventors: Harold Frank Greer, Andrew D. Beyer, Matthew D. Shaw, Daniel P. Cunnane
Publication number: 20210313185
Abstract: A method for etching a surface including obtaining a substrate comprising a material; reacting a surface of a substrate with a reactant, comprising a gas or a plasma, to form a reactive layer on the substrate, the reactive layer comprising a chemical compound including the reactant and the material; and wet etching or dissolving the reactive layer with a liquid wet etchant of solvent that selectively etches or dissolves the reactive layer but not the substrate.
Type: Application
Filed: April 6, 2021
Publication date: October 7, 2021
Applicant: California Institute of Technology
Inventor: Harold Frank Greer
Patent number: 10876276
Abstract: An atmospheric water generation system with high efficiency is based on a counter flowing heat exchanger including multiple cold channels, each cold channel surrounded by multiple hot channels. The hot and warm gases flow in opposite directions, allowing the cool dry air to contribute to cooling the warm humid air to the dew point. Thermoelectric or passive cooling of the warm humid air, and hydrophobic surfaces in a cyclone structure also contribute in increasing the efficiency of the water generation system.
Type: Grant
Filed: June 15, 2018
Date of Patent: December 29, 2020
Assignees: CALIFORNIA INSTITUTE OF TECHNOLOGY, PWIL INC.
Inventors: Harold Frank Greer, Peter Capak, Aria Anvar
Patent number: 10843923
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Grant
Filed: July 6, 2018
Date of Patent: November 24, 2020
Assignee: NANOCLEAR TECHNOLOGIES, INC.
Inventors: Harold Frank Greer, Ryan Morrow Briggs
Patent number: 10797189
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Grant
Filed: October 30, 2019
Date of Patent: October 6, 2020
Assignee: NANOCLEAR TECHNOLOGIES INC.
Inventors: Harold Frank Greer, Scott S. Harried, Ryan Morrow Briggs, Tony Lee
Publication number: 20200066927
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Application
Filed: October 30, 2019
Publication date: February 27, 2020
Inventors: Harold Frank GREER, Scott S. HARRIED, Ryan Morrow BRIGGS, Tony LEE
Publication number: 20200025981
Abstract: The optical scattering response of a textured substrate is altered by the addition of one or more layers of nanoparticles and/or coatings. The nanoparticles and/or coatings have a refractive index that is comparable, or higher, than the refractive index of the substrate. The scattering cross section of the substrate is reduced by partially or completely filling gaps in the substrate. A material having a hazy appearance to visible light is therefore rendered more transparent by the addition of nanoparticles.
Type: Application
Filed: July 19, 2019
Publication date: January 23, 2020
Inventors: Harold Frank GREER, Ryan Morrow BRIGGS, Sihan SHEN, Scott S. HARRIED, Tony LEE, Raymond LOBATON, Vahid MIRKHANI
Patent number: 10541266
Abstract: High-quality surface coatings, and techniques combining the atomic precision of molecular beam epitaxy and atomic layer deposition, to fabricate such high-quality surface coatings are provided. The coatings made in accordance with the techniques set forth by the invention are shown to be capable of forming silicon CCD detectors that demonstrate world record detector quantum efficiency (>50%) in the near and far ultraviolet (155 nm-300 nm). The surface engineering approaches used demonstrate the robustness of detector performance that is obtained by achieving atomic level precision at all steps in the coating fabrication process. As proof of concept, the characterization, materials, and exemplary devices produced are presented along with a comparison to other approaches.
Type: Grant
Filed: August 18, 2015
Date of Patent: January 21, 2020
Assignee: California Institute of Technology
Inventors: Frank Greer, Todd J. Jones, Shouleh Nikzad, Michael E. Hoenk
Patent number: 10510911
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Grant
Filed: October 3, 2018
Date of Patent: December 17, 2019
Assignee: NANOCLEAR TECHNOLOGIES INC.
Inventors: Harold Frank Greer, Scott S. Harried, Ryan Morrow Briggs, Tony Lee
Publication number: 20190355854
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Application
Filed: April 29, 2019
Publication date: November 21, 2019
Inventors: Harold Frank GREER, Rehan Rashid KAPADIA, Ryan Morrow BRIGGS
Publication number: 20190326454
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Application
Filed: July 2, 2019
Publication date: October 24, 2019
Inventors: Harold Frank GREER, Rehan Rashid KAPADIA, Ryan Morrow BRIGGS
Patent number: 10384810
Abstract: Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/?10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.
Type: Grant
Filed: July 15, 2015
Date of Patent: August 20, 2019
Assignee: California Institute of Technology
Inventors: Cecile Jung-Kubiak, Colleen M. Marrese-Reading, Victor E. White, Daniel W. Wilson, Matthew R. Dickie, Karl Y. Yee, Richard E. Muller, James E. Polk, John R. Anderson, Nima Rouhi, Frank Greer
Patent number: 10319868
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Grant
Filed: August 3, 2017
Date of Patent: June 11, 2019
Assignee: NANOCLEAR TECHNOLOGIES INC.
Inventors: Harold Frank Greer, Rehan Rashid Kapadia, Ryan Morrow Briggs
Publication number: 20190074389
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Application
Filed: October 3, 2018
Publication date: March 7, 2019
Inventors: Harold Frank GREER, Scott S. HARRIED, Ryan Morrow BRIGGS, Tony LEE
Publication number: 20190016593
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Application
Filed: July 6, 2018
Publication date: January 17, 2019
Inventors: Harold Frank GREER, Ryan Morrow BRIGGS
Publication number: 20180363277
Abstract: An atmospheric water generation system with high efficiency is based on a counter flowing heat exchanger including multiple cold channels, each cold channel surrounded by multiple hot channels. The hot and warm gases flow in opposite directions, allowing the cool dry air to contribute to cooling the warm humid air to the dew point. Thermoelectric or passive cooling of the warm humid air, and hydrophobic surfaces in a cyclone structure also contribute in increasing the efficiency of the water generation system.
Type: Application
Filed: June 15, 2018
Publication date: December 20, 2018
Inventors: Harold Frank GREER, Peter CAPAK, Aria ANVAR
Patent number: 10121919
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Grant
Filed: August 3, 2017
Date of Patent: November 6, 2018
Assignee: NANOCLEAR TECHNOLOGIES INC.
Inventors: Harold Frank Greer, Scott S. Harried, Ryan Morrow Briggs, Tony Lee
Publication number: 20180201395
Abstract: Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/?10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.
Type: Application
Filed: July 15, 2015
Publication date: July 19, 2018
Applicant: California Institute of Technology
Inventors: Cecile Jung-Kubiak, Colleen M. Marrese-Reading, Victor E. White, Daniel W. Wilson, Matthew R. Dickie, Karl Y. Yee, Richard E. Muller, James E. Polk, John R. Anderson, Nima Rouhi, Frank Greer
Publication number: 20180198006
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection or reflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Application
Filed: August 3, 2017
Publication date: July 12, 2018
Inventors: Harold Frank GREER, Scott S. HARRIED, Ryan Morrow BRIGGS, Tony LEE
Publication number: 20180194619
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Application
Filed: August 3, 2017
Publication date: July 12, 2018
Inventors: Harold Frank GREER, Ryan Morrow BRIGGS
Publication number: 20180198003
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Application
Filed: August 3, 2017
Publication date: July 12, 2018
Inventors: Harold Frank GREER, Rehan Rashid KAPADIA, Ryan Morrow BRIGGS
Patent number: 10017384
Abstract: The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.
Type: Grant
Filed: August 3, 2017
Date of Patent: July 10, 2018
Assignee: NANOCLEAR TECHNOLOGIES INC.
Inventors: Harold Frank Greer, Ryan Morrow Briggs
Publication number: 20170186935
Abstract: Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing low loss dielectric (LLD) layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500° C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.
Type: Application
Filed: December 29, 2015
Publication date: June 29, 2017
Applicant: Intermolecular, Inc.
Inventors: Joseph Anthony Bonetti, Frank Greer, Wenxian Zhu
Patent number: 9455393
Abstract: Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525° C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.
Type: Grant
Filed: December 28, 2015
Date of Patent: September 27, 2016
Assignee: Intermolecular, Inc.
Inventors: Ashish Bodke, Frank Greer, Mark Clark
Patent number: 9425376
Abstract: In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H2, or a combination to remove native oxides, etch residues, and other contaminants. Optionally, an O2 or O3 pre-clean may precede the sputter etch. When the electrode is clean, the tunnel barrier layer is deposited by ALD in-situ without further oxidant exposure.
Type: Grant
Filed: December 23, 2013
Date of Patent: August 23, 2016
Assignee: Intermolecular, Inc.
Inventors: Frank Greer, Andy Steinbach
Patent number: 9373497
Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
Type: Grant
Filed: February 5, 2013
Date of Patent: June 21, 2016
Assignee: Novellus Systems, Inc.
Inventors: David Chen, Haruhiro Harry Goto, Martina Su, Frank Greer, Shamsuddin Alokozai
Publication number: 20160133819
Abstract: Provided are superconducting circuits and methods of forming such circuits. A circuit may include a silicon containing low loss dielectric (LLD) layer formed by fluorine passivation of dangling bonds of silicon atoms in the layer. The LLD layer may be formed from silicon nitride or silicon oxide. For uniform passivation (e.g., uniform distribution of fluorine within the LLD layer), fluorine may be introduced while forming the LLD layer. For example, a fluorine containing precursor may be supplied into a deposition chamber together with a silicon containing precursor. Alternatively, the LLD layer may be formed as a stack of many thin sublayers, and each sublayer may be subjected to individual fluorine passivation. For example, low power plasma treatment or annealing in a fluorine containing environment may be used for this purpose. The concentration of fluorine in the LLD layer may be between about 0.5% atomic and 5% atomic.
Type: Application
Filed: December 29, 2015
Publication date: May 12, 2016
Applicant: Intermolecular, Inc.
Inventors: Frank Greer, Ashish Bodke
Patent number: 9324767
Abstract: Provided are superconducting tunnel junctions, such as Josephson tunnel junctions, and a method of fabricating thereof. A junction includes an insulator disposed between two superconductors. The junction may also include one or two interface layers, with each interface layer disposed between the insulator and one of the superconductors. The interface layer is configured to prevent oxygen from entering the adjacent superconductor during fabrication and operation of the junction. Furthermore, the interface layer may protect the insulator from the environment during handling and processing of the junction, thereby allowing vacuum breaks after the interface layer is formed as well as new integration schemes, such as depositing a dielectric layer and forming a trench in the dielectric layer for the second superconductor. In some embodiments, the junction may be annealed during its fabrication to move oxygen from the superconductors and/or from the insulator into the one or two interface layers.
Type: Grant
Filed: December 31, 2013
Date of Patent: April 26, 2016
Assignee: Intermolecular, Inc.
Inventors: Andrew Steinbach, Tony Bonetti, Frank Greer, Kurt Pang, Yun Wang
Patent number: 9312137
Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
Type: Grant
Filed: October 31, 2013
Date of Patent: April 12, 2016
Assignee: Intermolecular, Inc.
Inventors: Frank Greer, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, J Watanabe
Publication number: 20160093772
Abstract: Provided are methods of forming low resistivity contacts. Also provided are devices having such low resistive contacts. A method may include doping the surface of a structure, such as a gallium nitride layer. Specifically, a dopant containing layer is formed on the surface of the structure using, for example, atomic layer deposition (ALD). The dopant may magnesium. In some embodiments, the dopant containing layer also includes nitrogen. A capping layer may be then formed over the dopant containing layer to prevent dopant desorption. The stack including the structure with the dopant containing layer disposed on its surface is then annealed to transfer dopant from the dopant containing layer into the surface. After annealing, any remaining dopant containing layer is removed. When another component is later formed over the surface, a low resistivity contact is created between this other component and the doped structure.
Type: Application
Filed: September 30, 2014
Publication date: March 31, 2016
Inventors: Khaled Ahmed, Frank Greer, Andrew Steinbach
Patent number: 9281463
Abstract: Metal oxide tunnel barrier layers for superconducting tunnel junctions are formed by atomic layer deposition. Both precursors include a metal (which may be the same metal or may be different). The first precursor is a metal alkoxide with oxygen bonded to the metal, and the second precursor is an oxygen-free metal precursor with an alkyl-reactive ligand such as a halogen or methyl group. The alkyl-reactive ligand reacts with the alkyl group of the alkoxide, forming a detached by-product and leaving a metal oxide monolayer. The temperature is selected to promote the reaction without causing the metal alkoxide to self-decompose. The oxygen in the alkoxide precursor is bonded to a metal before entering the chamber and remains bonded throughout the reaction that forms the monolayer. Therefore, the oxygen used in this process has no opportunity to oxidize the underlying superconducting electrode.
Type: Grant
Filed: December 23, 2013
Date of Patent: March 8, 2016
Assignee: Intermolecular, Inc.
Inventors: Frank Greer, Andy Steinbach
Patent number: 9245743
Abstract: Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.
Type: Grant
Filed: December 17, 2013
Date of Patent: January 26, 2016
Assignee: Intermolecular, Inc.
Inventors: Khaled Ahmed, Frank Greer
Patent number: 9245793
Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated species. The activated species can be used to treat the surfaces of low-k and/or ultra low-k dielectric materials to facilitate improved deposition of diffusion barrier materials.
Type: Grant
Filed: December 19, 2013
Date of Patent: January 26, 2016
Assignee: Intermolecular, Inc.
Inventors: Ratsamee Limdulpaiboon, Frank Greer, Chi-I Lang, J. Watanabe, Wenxian Zhu
Publication number: 20160005786
Abstract: High-quality surface coatings, and techniques combining the atomic precision of molecular beam epitaxy and atomic layer deposition, to fabricate such high-quality surface coatings are provided. The coatings made in accordance with the techniques set forth by the invention are shown to be capable of forming silicon CCD detectors that demonstrate world record detector quantum efficiency (>50%) in the near and far ultraviolet (155 nm-300 nm). The surface engineering approaches used demonstrate the robustness of detector performance that is obtained by achieving atomic level precision at all steps in the coating fabrication process. As proof of concept, the characterization, materials, and exemplary devices produced are presented along with a comparison to other approaches.
Type: Application
Filed: August 18, 2015
Publication date: January 7, 2016
Inventors: Frank Greer, Todd J. Jones, Shouleh Nikzad, Michael E. Hoenk
Patent number: 9224783
Abstract: Defects in hydrogenated amorphous silicon are reduced by low-energy ion treatments and optional annealing. The treatments leave strongly-bonded hydrogen and other passivants in place, but increase the mobility of loosely-bonded and interstitially trapped hydrogen that would otherwise form unwanted two-level systems (TLS). The mobilized hydrogen atoms may be attracted to unused passivation sites or recombined into H2 gas and diffuse out of the deposited layer. The treatments also increase the density of the material. The optional anneal may partially crystallize the layer, further densify the layer, or both. The reduced number of defects and the increased crystallinity reduce the loss tangent of amorphous silicon dielectrics for superconducting microwave devices.
Type: Grant
Filed: December 23, 2013
Date of Patent: December 29, 2015
Assignee: Intermolecular, Inc.
Inventors: Frank Greer, Andy Steinbach, Wenxian Zhu
Patent number: 9224594
Abstract: Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface.
Type: Grant
Filed: November 18, 2013
Date of Patent: December 29, 2015
Assignee: Intermolecular, Inc.
Inventors: Kevin Kashefi, Frank Greer
Patent number: 9165971
Abstract: High-quality surface coatings, and techniques combining the atomic precision of molecular beam epitaxy and atomic layer deposition, to fabricate such high-quality surface coatings are provided. The coatings made in accordance with the techniques set forth by the invention are shown to be capable of forming silicon CCD detectors that demonstrate world record detector quantum efficiency (>50%) in the near and far ultraviolet (155 nm-300 nm). The surface engineering approaches used demonstrate the robustness of detector performance that is obtained by achieving atomic level precision at all steps in the coating fabrication process. As proof of concept, the characterization, materials, and exemplary devices produced are presented along with a comparison to other approaches.
Type: Grant
Filed: October 25, 2011
Date of Patent: October 20, 2015
Assignee: California Institute of Technology
Inventors: Frank Greer, Todd J. Jones, Shouleh Nikzad, Michael E. Hoenk
Patent number: 9131356
Abstract: A mobile electronic communications device includes a housing, a memory, a data entry mechanism, a display for visual data, at least one wireless transceiver configured to transmit and receive electromagnetic signals conforming to a plurality of wireless signaling protocols, and a controller. The controller is communicatively connected to the memory, data entry mechanism, and display; and is configured to send and receive data using the at least one wireless transceiver.
Type: Grant
Filed: December 29, 2010
Date of Patent: September 8, 2015
Assignee: Zipit Wireless, Inc.
Inventors: Rafael Heredia, Michael Crowe, Frank Greer, Joseph Ellis, Jordan Upham, William Matson
Patent number: 9123622
Abstract: A back-illuminated silicon photodetector has a layer of Al2O3 deposited on a region of a silicon oxide surface that is left uncovered, while deposition is inhibited in another region by a contact shadow mask. The Al2O3 layer is an antireflection coating. In addition, the Al2O3 layer can also provide a chemically resistant separation layer between the silicon oxide surface and additional antireflection coating layers. In one embodiment, the silicon photodetector has a delta-doped layer near (within a few nanometers of) the silicon oxide surface. The Al2O3 layer is expected to provide similar antireflection properties and chemical protection for doped layers fabricated using other methods, such as MBE, ion implantation and CVD deposition.
Type: Grant
Filed: February 21, 2014
Date of Patent: September 1, 2015
Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
Inventors: Michael E. Hoenk, Frank Greer, Shouleh Nikzad
Patent number: 9087864
Abstract: In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.
Type: Grant
Filed: December 19, 2013
Date of Patent: July 21, 2015
Assignee: Intermolecular, Inc.
Inventors: Chen-An Chen, Tony P. Chiang, Frank Greer, Martin Romero, James Tsung
Patent number: 9082927
Abstract: A tunnel barrier layer in a superconducting device, such as a Josephson junction, is made from catalytically grown silicon dioxide at a low temperature (<100 C, e.g., 20-30 C) that does not facilitate oxidation or silicide formation at the superconducting electrode interface. The tunnel barrier begins as a silicon layer deposited on a superconducting electrode and covered by a thin, oxygen-permeable catalytic layer. Oxygen gas is dissociated on contact with the catalytic layer, and the resulting oxygen atoms pass through the catalytic layer to oxidize the underlying silicon. The reaction self-limits when all the silicon is converted to silicon dioxide.
Type: Grant
Filed: December 20, 2013
Date of Patent: July 14, 2015
Assignee: Intermolecular, Inc.
Inventors: Dipankar Pramanik, Frank Greer, Andrew Steinbach
Patent number: 9076651
Abstract: SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.
Type: Grant
Filed: December 20, 2013
Date of Patent: July 7, 2015
Assignee: Intermolecular, Inc.
Inventors: Khaled Ahmed, Frank Greer, Raj Jammy
Publication number: 20150179914
Abstract: A interconnect structure for superconducting devices uses a material with a high melting point for the superconductive wiring; examples include refractory metals such as niobium. Because the wiring is tolerant of high temperatures, the interlayer dielectric (e.g., amorphous silicon with or without small amounts of passivants such as hydrogen or fluorine) may be subjected to rapid thermal annealing to reduce defects by driving off excess hydrogen, and optionally partially crystallizing the material.
Type: Application
Filed: December 23, 2013
Publication date: June 25, 2015
Applicant: Intermolecular Inc.
Inventors: Frank Greer, Andy Steinbach, Wenxian Zhu
Publication number: 20150179438
Abstract: SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.
Type: Application
Filed: December 20, 2013
Publication date: June 25, 2015
Applicant: Intermolecular, Inc.
Inventors: Khaled Ahmed, Frank Greer, Raj Jammy
Publication number: 20150179487
Abstract: In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.
Type: Application
Filed: December 19, 2013
Publication date: June 25, 2015
Applicant: Intermolecular, Inc.
Inventors: Chen-An Chen, Tony P. Chiang, Frank Greer, Martin Romero, James Tsung
Publication number: 20150176124
Abstract: Systems and methods for rapid generation of ALD saturation curves using segmented spatial ALD are disclosed. Methods include introducing a substrate, having a plurality of substrate segment regions, into a processing chamber. The substrate may be disposed upon a pedestal within the chamber. Sequentially exposing the plurality of segment regions to a precursor within the chamber at a first processing temperature. Afterwards, purging the precursor from the chamber and then sequentially exposing each plurality of segment regions to a reactant within the chamber at the first processing temperature. Afterwards, purging the reactant from the chamber. Repeat sequentially exposing the plurality of segment regions to the precursor and the reactant for a plurality of cycles. Each segment region may be sequentially exposed to the precursor for a unique processing time. The pedestal may be rotated prior to exposing each next segment region to the precursor and the reactant.
Type: Application
Filed: December 19, 2013
Publication date: June 25, 2015
Applicant: Intermolecular, Inc.
Inventors: Frank Greer, Khaled Ahmed, Chen-An Chen, Wenxian Zhu
Publication number: 20150179918
Abstract: In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H2, or a combination to remove native oxides, etch residues, and other contaminants. Optionally, an O2 or O3 pre-clean may precede the sputter etch. When the electrode is clean, the tunnel barrier layer is deposited by ALD in-situ without further oxidant exposure.
Type: Application
Filed: December 23, 2013
Publication date: June 25, 2015
Applicant: Intermolecular Inc.
Inventors: Frank Greer, Andy Steinbach
Publication number: 20150179436
Abstract: Defects in hydrogenated amorphous silicon are reduced by low-energy ion treatments and optional annealing. The treatments leave strongly-bonded hydrogen and other passivants in place, but increase the mobility of loosely-bonded and interstitially trapped hydrogen that would otherwise form unwanted two-level systems (TLS). The mobilized hydrogen atoms may be attracted to unused passivation sites or recombined into H2 gas and diffuse out of the deposited layer. The treatments also increase the density of the material. The optional anneal may partially crystallize the layer, further densify the layer, or both. The reduced number of defects and the increased crystallinity reduce the loss tangent of amorphous silicon dielectrics for superconducting microwave devices.
Type: Application
Filed: December 23, 2013
Publication date: June 25, 2015
Applicant: Intermolecular Inc.
Inventors: Frank Greer, Andy Steinbach, Wenxian Zhu
Publication number: 20150179917
Abstract: Metal oxide tunnel barrier layers for superconducting tunnel junctions are formed by atomic layer deposition. Both precursors include a metal (which may be the same metal or may be different). The first precursor is a metal alkoxide with oxygen bonded to the metal, and the second precursor is an oxygen-free metal precursor with an alkyl-reactive ligand such as a halogen or methyl group. The alkyl-reactive ligand reacts with the alkyl group of the alkoxide, forming a detached by-product and leaving a metal oxide monolayer. The temperature is selected to promote the reaction without causing the metal alkoxide to self-decompose. The oxygen in the alkoxide precursor is bonded to a metal before entering the chamber and remains bonded throughout the reaction that forms the monolayer. Therefore, the oxygen used in this process has no opportunity to oxidize the underlying superconducting electrode.
Type: Application
Filed: December 23, 2013
Publication date: June 25, 2015
Applicant: Intermolecular Inc.
Inventors: Frank Greer, Andy Steinbach
Publication number: 20150179915
Abstract: A dielectric for superconducting electronics (e.g., amorphous silicon, silicon oxide, or silicon nitride) is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. A fluorinant (gas or plasma) is injected into a process chamber, either continuously or as a series of pulses, while the dielectric is being formed by chemical vapor deposition on a substrate. To further reduce defects, the silicon may be deposited from a silicon precursor that includes multiple co-bonded silicon atoms, such as disilane or trisilane.
Type: Application
Filed: December 23, 2013
Publication date: June 25, 2015
Applicant: INTERMOLECULAR, INC.
Inventors: Frank Greer, Sergey Barabash, Dipankar Pramanik, Andrew Steinbach
Publication number: 20150179509
Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated species. The activated species can be used to treat the surfaces of low-k and/or ultra low-k dielectric materials to facilitate improved deposition of diffusion barrier materials.
Type: Application
Filed: December 19, 2013
Publication date: June 25, 2015
Applicant: Intermolecular, Inc.
Inventors: Ratsamee Limdulpaiboon, Frank Greer, Chi-I Lang, J. Watanabe, Wenxian Zhu
Publication number: 20150179916
Abstract: A tunnel barrier layer in a superconducting device, such as a Josephson junction, is made from catalytically grown silicon dioxide at a low temperature (<100 C, e.g., 20-30 C) that does not facilitate oxidation or silicide formation at the superconducting electrode interface. The tunnel barrier begins as a silicon layer deposited on a superconducting electrode and covered by a thin, oxygen-permeable catalytic layer. Oxygen gas is dissociated on contact with the catalytic layer, and the resulting oxygen atoms pass through the catalytic layer to oxidize the underlying silicon. The reaction self-limits when all the silicon is converted to silicon dioxide.
Type: Application
Filed: December 20, 2013
Publication date: June 25, 2015
Applicant: Intermolecular, Inc.
Inventors: Dipankar Pramanik, Frank Greer, Andrew Steinbach
Publication number: 20150179508
Abstract: Embodiments described herein provide tantalum-based copper barriers and methods for forming such barriers. A dielectric body is provided. A first layer is formed above the dielectric body. The first layer includes tantalum. A second layer is formed above the first layer. The second layer includes manganese. A third layer is formed above the second layer. The third layer includes copper.
Type: Application
Filed: December 23, 2013
Publication date: June 25, 2015
Applicant: INTERMOLECULAR INC.
Inventors: Edwin Adhiprakasha, Sean Barstow, Frank Greer, Wenxian Zhu
Publication number: 20150140834
Abstract: Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface.
Type: Application
Filed: November 18, 2013
Publication date: May 21, 2015
Applicant: Intermolecular Inc.
Inventors: Kevin Kashefi, Frank Greer
Publication number: 20150132938
Abstract: Methods are provided for the deposition of high-k gate dielectric materials which are doped with fluorine and/or nitrogen to improve the performance and reliability. The high-k dielectric materials may include at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium aluminum oxide, titanium oxide, titanium silicon oxide, or titanium aluminum oxide. The fluorine dopant is provided from a layer including titanium nitride or amorphous silicon, where the layer is doped with at least one of fluorine or nitrogen. The dopants diffuse into the high-k dielectric material during a subsequent anneal process.
Type: Application
Filed: November 13, 2013
Publication date: May 14, 2015
Applicant: Intermolecular, Inc.
Inventors: Khaled Ahmed, Frank Greer
Publication number: 20150118828
Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
Type: Application
Filed: October 31, 2013
Publication date: April 30, 2015
Applicant: Intermolecular Inc.
Inventors: Frank Greer, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, J Watanabe
Patent number: 8975706
Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.
Type: Grant
Filed: December 19, 2013
Date of Patent: March 10, 2015
Assignee: Intermolecular, Inc.
Inventors: Khaled Ahmed, Frank Greer
Publication number: 20150064361
Abstract: Irradiation with ultraviolet (UV) light during atomic layer deposition (ALD) can be used to cleave unwanted bonds on the layer being formed (e.g., trapped precursor ligands or process-gas molecules). Alternatively, the UV irradiation can be used to excite the targeted bonds so they may be more easily cleaved by other means. The use of UV may enable the formation of low-defect-density films at lower deposition temperatures (e.g., <250 C), or reduce the need for a high-temperature post-deposition anneal, improving the quality of devices formed on heat-sensitive materials such as germanium.
Type: Application
Filed: September 4, 2013
Publication date: March 5, 2015
Applicant: Intermolecular Inc.
Inventors: Frank Greer, Amol Joshi, Kevin Kashefi
Publication number: 20150041912
Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.
Type: Application
Filed: December 19, 2013
Publication date: February 12, 2015
Applicant: Intermolecular, Inc.
Inventors: Khaled Ahmed, Frank Greer
Publication number: 20150035085
Abstract: Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.
Type: Application
Filed: December 17, 2013
Publication date: February 5, 2015
Applicant: Intermolecular Inc.
Inventors: Khaled Ahmed, Frank Greer
Patent number: 8906791
Abstract: Methods, apparatus, and systems for depositing materials with gaseous precursors are provided. In certain implementations, the methods involve providing a wafer substrate to a chamber of an apparatus. The apparatus includes a showerhead to deliver a gas to the chamber, a volume, and an isolation valve between the volume and the showerhead. A gas is delivered the volume when the isolation valve is closed, pressurizing the volume. The isolation valve is opened to allow the gas to flow to the showerhead when the gas is being delivered to the volume. A material is formed on the wafer substrate using the gas. In some implementations, releasing the pressurized gas from the volume reduces the duration of time to develop a spatially uniform gas flow across the showerhead.
Type: Grant
Filed: June 3, 2011
Date of Patent: December 9, 2014
Assignee: Novellus Systems, Inc.
Inventors: Kie-Jin Park, Karl Leeser, Frank Greer, David Cohen
Patent number: 8906709
Abstract: Provided are methods of high productivity combinatorial (HPC) inspection of semiconductor substrates. A substrate includes two layers of dissimilar materials interfacing each other, such as a stack of a silicon bottom layer and an indium gallium arsenide top layer. The dissimilar materials have one or more of thermal, structural, and lattice mismatches. As a part of the inspection, the top layer is etched in a combinatorial manner. Specifically, the top layer is divided into multiple different site-isolated regions. One such region may be etched using different process conditions from another region. Specifically, etching temperature, etching duration and/or etchant composition may vary among the site-isolated regions. After combinatorial etching, each region is inspected to determine its etch-pit density (EPD) value. These values may be then analyzed to determine an overall EPD value for the substrate, which may involve discarding EPD values for over-etched and under-etched regions.
Type: Grant
Filed: December 23, 2013
Date of Patent: December 9, 2014
Assignee: Intermolecular, Inc.
Inventors: Khaled Ahmed, Frank Greer, George Mirth, Zhi-Wen Sun
Patent number: 8901677
Abstract: A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition of the dielectric overlayer to prevent uncontrolled regrowth of native oxide. The monolayer of GeO2 promotes uniform nucleation of the dielectric overlayer, but it too thin to appreciably impact the effective oxide thickness of the dielectric overlayer.
Type: Grant
Filed: March 5, 2014
Date of Patent: December 2, 2014
Assignee: Intermolecular, Inc.
Inventors: Frank Greer, Edwin Adhiprakasha, Chi-I Lang, Ratsamee Limdulpaiboon, Sandip Niyogi, Kurt Pang, J. Watanabe
Publication number: 20140335823
Abstract: A mobile electronic communications device includes a housing, a memory, a data entry mechanism, a display for visual data, at least one wireless transceiver configured to transmit and receive electromagnetic signals conforming to a plurality of wireless signaling protocols, and a controller. The controller is communicatively connected to the memory, data entry mechanism, and display; and is configured to send and receive data using the at least one wireless transceiver.
Type: Application
Filed: December 29, 2010
Publication date: November 13, 2014
Applicant: ZIPIT WIRELESS, INC.
Inventors: Rafael Heredia, Michael Crowe, Frank Greer, Joseph Ellis, Jordan Upham, William Matson
Publication number: 20140252565
Abstract: A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition of the dielectric overlayer to prevent uncontrolled regrowth of native oxide. The monolayer of GeO2 promotes uniform nucleation of the dielectric overlayer, but it too thin to appreciably impact the effective oxide thickness of the dielectric overlayer.
Type: Application
Filed: March 5, 2014
Publication date: September 11, 2014
Applicant: Intermolecular, Inc.
Inventors: Frank Greer, Edwin Adhiprakasha, Chi-I Lang, Ratsamee Limdulpaiboon, Sandip Niyogi, Kurt Pang, J. Watanabe
Patent number: 8828852
Abstract: Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3+NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.
Type: Grant
Filed: December 10, 2010
Date of Patent: September 9, 2014
Assignee: California Institute of Technology
Inventors: Michael E. Hoenk, Shoulch Nikzad, Todd J. Jones, Frank Greer, Alexander G. Carver
Publication number: 20140167198
Abstract: A back-illuminated silicon photodetector has a layer of Al2O3 deposited on a region of a silicon oxide surface that is left uncovered, while deposition is inhibited in another region by a contact shadow mask. The Al2O3 layer is an antireflection coating. In addition, the Al2O3 layer can also provide a chemically resistant separation layer between the silicon oxide surface and additional antireflection coating layers. In one embodiment, the silicon photodetector has a delta-doped layer near (within a few nanometers of) the silicon oxide surface. The Al2O3 layer is expected to provide similar antireflection properties and chemical protection for doped layers fabricated using other methods, such as MBE, ion implantation and CVD deposition.
Type: Application
Filed: February 21, 2014
Publication date: June 19, 2014
Inventors: Michael E. Hoenk, Frank Greer, Shouleh Nikzad
Patent number: 8697474
Abstract: Embodiments of the invention provide for fabricating a filter, for electromagnetic radiation, in at least three ways, including (1) fabricating integrated thin film filters directly on a detector; (2) fabricating a free standing thin film filter that may be used with a detector; and (3) treating an existing filter to improve the filter's properties.
Type: Grant
Filed: January 13, 2011
Date of Patent: April 15, 2014
Assignee: California Institute of Technology
Inventors: Frank Greer, Shouleh Nikzad
Patent number: 8680637
Abstract: A back-illuminated silicon photodetector has a layer of Al2O3 deposited on a silicon oxide surface that receives electromagnetic radiation to be detected. The Al2O3 layer has an antireflection coating deposited thereon. The Al2O3 layer provides a chemically resistant separation layer between the silicon oxide surface and the antireflection coating. The Al2O3 layer is thin enough that it is optically innocuous. Under deep ultraviolet radiation, the silicon oxide layer and the antireflection coating do not interact chemically. In one embodiment, the silicon photodetector has a delta-doped layer near (within a few nanometers of) the silicon oxide surface. The Al2O3 layer is expected to provide similar protection for doped layers fabricated using other methods, such as MBE, ion implantation and CVD deposition.
Type: Grant
Filed: June 23, 2011
Date of Patent: March 25, 2014
Assignee: California Institute of Technology
Inventors: Michael E. Hoenk, Frank Greer, Shouleh Nikzad
Publication number: 20130157465
Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
Type: Application
Filed: February 5, 2013
Publication date: June 20, 2013
Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
Patent number: 8435895
Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
Type: Grant
Filed: April 4, 2007
Date of Patent: May 7, 2013
Assignee: Novellus Systems, Inc.
Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
Publication number: 20120168891
Abstract: High-quality surface coatings, and techniques combining the atomic precision of molecular beam epitaxy and atomic layer deposition, to fabricate such high-quality surface coatings are provided. The coatings made in accordance with the techniques set forth by the invention are shown to be capable of forming silicon CCD detectors that demonstrate world record detector quantum efficiency (>50%) in the near and far ultraviolet (155 nm-300 nm). The surface engineering approaches used demonstrate the robustness of detector performance that is obtained by achieving atomic level precision at all steps in the coating fabrication process. As proof of concept, the characterization, materials, and exemplary devices produced are presented along with a comparison to other approaches.
Type: Application
Filed: October 25, 2011
Publication date: July 5, 2012
Applicant: California Institute of Technology
Inventors: Frank Greer, Todd J. Jones, Shouleh Nikzad, Michael E. Hoenk
Patent number: 8163094
Abstract: A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.
Type: Grant
Filed: July 23, 2009
Date of Patent: April 24, 2012
Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
Inventors: H. Frank Greer, Todd J. Jones, Richard P. Vasquez, Michael E. Hoenk, Matthew R. Dickie, Shouleh Nikzad
Publication number: 20110316110
Abstract: A back-illuminated silicon photodetector has a layer of Al2O3 deposited on a silicon oxide surface that receives electromagnetic radiation to be detected. The Al2O3 layer has an antireflection coating deposited thereon. The Al2O3 layer provides a chemically resistant separation layer between the silicon oxide surface and the antireflection coating. The Al2O3 layer is thin enough that it is optically innocuous. Under deep ultraviolet radiation, the silicon oxide layer and the antireflection coating do not interact chemically. In one embodiment, the silicon photodetector has a delta-doped layer near (within a few nanometers of) the silicon oxide surface. The Al2O3 layer is expected to provide similar protection for doped layers fabricated using other methods, such as MBE, ion implantation and CVD deposition.
Type: Application
Filed: June 23, 2011
Publication date: December 29, 2011
Applicant: California Institute of Technology
Inventors: Michael E. Hoenk, Frank Greer, Shouleh Nikzad
Publication number: 20110300716
Abstract: Methods, apparatus, and systems for depositing materials with gaseous precursors are provided. In certain implementations, the methods involve providing a wafer substrate to a chamber of an apparatus. The apparatus includes a showerhead to deliver a gas to the chamber, a volume, and an isolation valve between the volume and the showerhead. A gas is delivered the volume when the isolation valve is closed, pressurizing the volume. The isolation valve is opened to allow the gas to flow to the showerhead when the gas is being delivered to the volume. A material is formed on the wafer substrate using the gas. In some implementations, releasing the pressurized gas from the volume reduces the duration of time to develop a spatially uniform gas flow across the showerhead.
Type: Application
Filed: June 3, 2011
Publication date: December 8, 2011
Inventors: Kie-Jin PARK, Karl LEESER, Frank GREER, David COHEN
Patent number: 8053372
Abstract: The present invention relates to an enhanced cyclic deposition process suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. The deposition enhancement is derived from ions generated in a plasma. The techniques described reduce the time required for plasma stabilization, thereby reducing deposition time and improving efficiency.
Type: Grant
Filed: September 12, 2006
Date of Patent: November 8, 2011
Assignee: Novellus Systems, Inc.
Inventors: Frank Greer, Karl Leeser
Publication number: 20110169119
Abstract: Embodiments of the invention provide for fabricating a filter, for electromagnetic radiation, in at least three ways, including (1) fabricating integrated thin film filters directly on a detector; (2) fabricating a free standing thin film filter that may be used with a detector; and (3) treating an existing filter to improve the filter's properties.
Type: Application
Filed: January 13, 2011
Publication date: July 14, 2011
Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
Inventors: Frank Greer, Shouleh Nikzad
Publication number: 20110169160
Abstract: A method, apparatus, system, and device provide the ability to form one or more solder bumps on one or more materials. The solder bumps are reflowed. During the reflowing, the solder bumps are monitored in real time. The reflow is controlled in real time, thereby controlling a morphology of each of the solder bumps. Further, the wetting of the solder bumps to a surface of the materials is controlled in real time.
Type: Application
Filed: January 13, 2011
Publication date: July 14, 2011
Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
Inventors: Frank Greer, Todd J. Jones, Shouleh Nikzad, Thomas J. Cunningham, Edward R. Blazejewski, Matthew R. Dickie, Michael E. Hoenk
Publication number: 20110140246
Abstract: Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3+NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.
Type: Application
Filed: December 10, 2010
Publication date: June 16, 2011
Applicant: California Institute of Technology
Inventors: Michael E. Hoenk, Shouleh Nikzad, Todd J. Jones, Frank Greer, Alexander G. Carver
Patent number: 7871678
Abstract: The present invention relates to an enhanced cyclic deposition process suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. The technique increases the chemical reactivity of a precursor used in the process.
Type: Grant
Filed: September 12, 2006
Date of Patent: January 18, 2011
Assignee: Novellus Systems, Inc.
Inventors: Frank Greer, Karl Leeser
Patent number: 7855147
Abstract: Copper seed layers are formed on diffusion barrier layers (e.g., on Ta, and TaNx layers) without significant agglomeration of copper, with the use of an engineered barrier layer/seed layer interface. The engineered interface includes an adhesion layer, in which copper atoms are physically trapped and are prevented from migrating and agglomerating. The adhesion layer can include between about 20-80% atomic of copper. The copper atoms of the adhesion layer are exposed during deposition of a copper seed layer and serve as the nucleation sites for the deposited copper. Thin, continuous, and conformal seed layers can be deposited on top of the adhesion layer. The trapping of copper within the adhesion layer is achieved by intermixing diffusion barrier and seed layer materials using PVD and/or ALD.
Type: Grant
Filed: May 24, 2007
Date of Patent: December 21, 2010
Assignee: Novellus Systems, Inc.
Inventors: Alexander Dulkin, Asit Rairkar, Frank Greer, Anshu A. Pradhan, Robert Rozbicki
Publication number: 20080248656
Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
Type: Application
Filed: April 4, 2007
Publication date: October 9, 2008
Applicant: NOVELLUS SYSTEMS, INC.
Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
Publication number: 20060239650
Abstract: Control of audio/video equipment is provided by an apparatus constructed like a computer, with audio and video subsystems. The audio subsystem includes a programmable analog mixer and several analog and digital multiplexers to route and mix multiple inputs to multiple outputs. Databases are stored in computer mass storage to record preferences for playback of digital versatile discs, compact discs and audio files stored in the mass storage device, such as MP3 files. The playback preferences may include video output format, language, surround sound mode, etc. for DVDs and surround sound effects for CDs and audio files.
Type: Application
Filed: June 19, 2006
Publication date: October 26, 2006
Applicant: Digital Networks North America, Inc.
Inventors: Rafael Heredia, Frank Greer, Randolph Young, Sean Priddy, Michael Dean
Patent number: 6993722
Abstract: A user interface system, method and computer program product permits selection of predetermined device application modes in a television set system and checking the activation status of other application modes. If active modes are identified which are incompatible with the selected active mode, then these other active modes are halted. If compatible active modes are identified, then these remain concurrently active, with particularized adaptations being made. The user interface is particularly adapted for use with a set-top box environment using a TV set as a user display.
Type: Grant
Filed: February 7, 2000
Date of Patent: January 31, 2006
Assignee: Cirrus Logic, Inc.
Inventors: Frank Greer, Sean Priddy, Rafael Heredia
Publication number: 20050144237
Abstract: An instant messaging terminal manages multiple conversation sessions across multiple instant messaging services. The terminal includes a display for conversation session windows, a data entry device, a communications module for wireless network communication, and a control module for coordinating network access and controlling conversation session management. The data entry device includes programmable keys for emoticons and the control module automates the generation of a key sequence for generation of a graphical symbol that is compatible with the service being used by a message recipient.
Type: Application
Filed: May 14, 2004
Publication date: June 30, 2005
Inventors: Rafael Heredia, Frank Greer, Michael Dean